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RT8057A 1 ds8057a-00 march 2011 www.richtek.com pin configurations ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. (top view) wdfn-6sl 2x2 2.25mhz 1a synchronous step-down converter general description the RT8057A is a high efficiency pulse-width-modulated (pwm) step-down dc/dc converter, capable of delivering 1a output current over a wide input voltage range from 2.7v to 5.5v. the RT8057A is ideally suited for portable electronic devices that are powered from 1-cell li-ion battery or from other power sources such as cellular phones, pdas, hand-held devices, game console and related accessories. the internal synchronous rectifier with low r ds(on) dramatically reduces conduction loss at pwm mode. no external schottky diode is required in practical applications. the RT8057A enters low dropout mode when normal pulse -width mode cannot provide regulated output voltage by continuously turning on the upper p-mosfet. the RT8057A enters shut-down mode and consumes less than 1 a when the en pin is pulled low. the switching ri pple is easily smoothed-ou t by small package filtering elements due to a fixed operating frequency of 2.25mhz. the RT8057A is available in a small wdfn-6sl 2x2 package. features zz zz z 2.7v to 5.5v wide input operation range zz zz z 2.25mhz fixed-frequency pwm operation zz zz z up to 1a output current zz zz z up to 90% efficiency zz zz z 0.6v reference allows low output voltage zz zz z internal soft-start zz zz z no schottky diode required zz zz z internal compensation to reduce external components zz zz z low dropout operation : 100% duty cycle zz zz z rohs compliant and halogen free applications z portable instruments z game console and accessories z microprocessors and dsp core supplies z cellular phones z wireless and dsl modems z pc cards lx nc gnd vin en fb 5 4 1 2 3 6 gnd 7 marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. vin en gnd lx fb 4 23 5 tsot-23-5 RT8057A package type qw : wdfn-6sl 2x2 (w-type) j5 : tsot-23-5 lead plating system g : green (halogen free and pb free) pin 1 orientation (2) : quadrant 2, follow eia-481-d (for wdfn-6sl 2x2 only) (2)
RT8057A 2 ds8057a-00 march 2011 www.richtek.com function pin description pin no. pin name pin function wdfn-6sl 2x2 tsot-23-5 1 5 lx switch node. connect to the external inductor. 2 -- nc no internal connection. connect to gnd. 3 4 fb feedback pin. connect to the external resistor divider. the fb reference voltage is 0.6v typically. 4 3 en chip enable (active high). 5 1 vin power input. connect to the input capacitor. 6, 7 (exposed pad) 2 gnd power gnd. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dis sipation. function block diagram typical application circuit comp r c r s1 r s2 en vin lx fb uvlo & power good detector v ref slope compensation current sense osc & shutdown control current limit detector driver control logic pwm comparator error amplifier gnd vin lx RT8057A en fb v in v out l1 c out r1 r2 c1 gnd 2.2h 10pf 10f c in 4.7f 680k 240k 2.3v
RT8057A 3 ds8057a-00 march 2011 www.richtek.com absolute maximum ratings (note 1) z supply input voltage, v in ------------------------------------------------------------------------------------------------ 6.5v z power dissipation, p d @ t a = 25 c wdfn-6sl 2x2 ------------------------------------------------------------------------------------------------------------ 0.833w tsot-23-5 ------------------------------------------------------------------------------------------------------------------- 0.625w z package thermal resistance (note 2) wdfn-6sl 2x2, ja ------------------------------------------------------------------------------------------------------- 120 c/w wdfn-6sl 2x2, jc ------------------------------------------------------------------------------------------------------ 8.2 c/w tsot-23-5, ja ------------------------------------------------------------------------------------------------------------- 160 c/w z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm -------------------------------------------------------------------------------------------------------------------------- 2k v mm ---------------------------------------------------------------------------------------------------------------------------- 2 00v recommended operating conditions (note 4) z supply input voltage, v in ------------------------------------------------------------------------------------------------ 2.7v to 5.5v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics parameter symbol test conditions min typ max unit output current i out v in = 2.7v to 5.5v -- -- 1 a quiescent current i q i out = 0ma -- 81 -- ? ? (v in = 3.6v, t a = 25 c unless otherwise specified)
RT8057A 4 ds8057a-00 march 2011 www.richtek.com note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. the reference voltage accuracy is 2.5% at recommended ambient temperature range, guaranteed by design.
RT8057A 5 ds8057a-00 march 2011 www.richtek.com typical operating characteristics output voltage vs. input voltage 2.22 2.24 2.26 2.28 2.30 2.32 2.34 2.36 2.38 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) output voltage (v) v out = 2.3v, i out = 0a efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 output current (a) efficiency (%) v out = 2.3v v in = 5v v in = 3.3v frequency vs. input voltage 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) frequency (mhz) 1 v in = 5v, v out = 2.3v, i out = 0.2a output current limit vs. input voltage 1.0 1.1 1.2 1.3 1.4 1.5 1.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) output current limit (a ) v out = 2.3v frequency vs. temperature 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 -50 -25 0 25 50 75 100 125 temperature (c) frequency (mhz) 1 v in = 5v v in = 3.3v v out = 2.3v, i out = 0.2a output current limit vs. temperature 1.0 1.1 1.2 1.3 1.4 1.5 1.6 -50 -25 0 25 50 75 100 125 temperature (c) output current limit (a) v in = 5v, v out = 2.3v
RT8057A 6 ds8057a-00 march 2011 www.richtek.com reference voltage vs. temperature 0.592 0.594 0.596 0.598 0.600 0.602 0.604 0.606 0.608 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) v in = 5v, v out = 2.3v load transient response time (100 s/div) v in = 5v, v out = 2.3v, i out = 0a to 1a i out (500ma/div) v out (100mv/div) output ripple v in = 3.3v, v out = 2.3v, i out = 1a time (250ns/div) v lx (5v/div) v out (5mv/div) output voltage vs. temperature 2.25 2.26 2.27 2.28 2.29 2.30 2.31 2.32 2.33 2.34 2.35 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 5v, v out = 2.3v, i out = 0a output ripple time (250ns/div) v lx (5v/div) v out (5mv/div) v in = 5v, v out = 2.3v, i out = 1a load transient response time (100 s/div) i out (500ma/div) v out (100mv/div) v in = 5v, v out = 2.3v, i out = 0.4a to 1a
RT8057A 7 ds8057a-00 march 2011 www.richtek.com uvlo vs. temperature 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 -50 -25 0 25 50 75 100 125 temperature (c) uvlo (v) v out = 2.3v rising falling power on from en time (100 s/div) v en (2v/div) v out (2v/div) i out (500ma/div) v in = 5v, v out = 2.3v, i out = 1a power off from en time (100 s/div) v en (2v/div) v out (2v/div) i out (500ma/div) v in = 5v, v out = 2.3v, i out = 1a output voltage vs. output current 2.26 2.27 2.28 2.29 2.30 2.31 2.32 2.33 2.34 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output current (a) output voltage (v) v in = 5v, v out = 2.3v en threshold vs. temperature 0.60 0.62 0.64 0.66 0.68 0.70 0.72 0.74 0.76 0.78 0.80 -50 -25 0 25 50 75 100 125 temperature (c) en threshold (v) v in = 5v, v out = 2.3v rising falling
RT8057A 8 ds8057a-00 march 2011 www.richtek.com application information the basic RT8057A application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . output voltage setting the output voltage is set by an external resistive divider according to the following equation : out ref r1 vv x (1) r2 =+ soft-start the RT8057A contains an internal soft-start clamp that gradually raises the clamp on the fb pin. 100% duty cycle operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle, eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-mosfet and the inductor. low supply operation the RT8057A is designed to operate down to an input supply voltage of 2.7v. one important consideration at low input supply voltages is that the r ds(on) of the p- channel and n-channel power switches increases. the user should calculate the power dissipation when the RT8057A is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. under voltage protection (uvp) the output voltage can be continuously monitored for under voltage protection. when the output voltage is less than 33% of its set voltage threshold after ocp occurs, the under voltage protection circuit will be triggered to auto re-softstart. input voltage over voltage protection (v in ovp) when the input voltage (v in ) is higher than 6v, v in ovp will be triggered and the ic stops switching. once the input voltage drops below 6v, the ic will return to normal operation. output over voltage protection (v out ovp) when the output voltage exceeds more than 5% of the nominal reference voltage, the feedback loop forces the internal switches off within 50 s. therefore, the output over voltage protection is automatically triggered by the loop. short circuit protection when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. a current runaway detector is used to monitor inductor current. as current increases beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring. component supplier series inductance ( h) dcr (m ) current rating (ma) dimensions (mm) taiyo yuden nr4018 t2r2m 2.2 table 1. inductors gnd fb RT8057A r1 r2 v out
RT8057A 9 ds8057a-00 march 2011 www.richtek.com c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : out in rms out(max) in out v v ii 1 vv =? this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst case condition is commonly used for design because even significant deviations do not result in much difference. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple, v out , is determined by : out l out 1 viesr 8fc ?? ?? + ?? ?? the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr, but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density, but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics, but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. table 2. capacitors for c in and c out component supplier part no. capacitance ( f) case size murata grm31cr71a475ka01 4.7 f 1206 murata grm31cr71a106ka01 10 f 1206 thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance.
RT8057A 10 ds8057a-00 march 2011 www.richtek.com figure 2. derating curve for the RT8057A package layout considerations follow the pcb layout guidelines for optimal performance of the RT8057A. ` connect the terminal of the input capacitor(s), c in , as close as possible to the vin pin. this capacitor provides the ac current into the internal power mosfets. ` lx node experiences high frequency voltage swing and should be kept within a small area. keep all sensitive small-signal nodes away from the lx node to prevent stray capacitive noise pick up. ` flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. connect the copper areas to any dc net (v in , v out , gnd, or any other dc rail in the system). ` connect the fb pin directly to the feedback resistors. the resistive voltage divider must be connected between v out and gnd. (a) for wdfn-6sl 2x2 package lx nc gnd vin en fb 5 4 1 2 3 6 gnd 7 v out l1 v out c1 r1 r2 c out c in input capacitor must be placed as close to the ic as possible. lx should be connected to inductor by wide and short trace. keep sensitive components away from this trace. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) four-layer pcb wdfn-6sl 2x2 tsot-23-5 vin gnd en lx fb 4 2 3 5 1 c in v out gnd c out r1 r2 input capacitor must be placed as close to the ic as possible. lx should be connected to inductor by wide and short trace. keep sensitive components away from this trace. l1 figure 3. pcb layout guide for recommended operating condition specifications of the RT8057A, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn- 6sl 2x2 package, the thermal resistance, ja , is 120 c/ w on a standard jedec 51-7 four-layer thermal test board. for tsot-23-5 package, the thermal resistance, ja , is 160 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (120 c/w) = 0.833w for wdfn-6sl 2x2 package p d(max) = (125 c ? 25 c) / (160 c/w) = 0.625w for tsot-23-5 package he maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT8057A packages, the derating curve in figure 1 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. (a) for tsot-23-5 package
RT8057A 11 ds8057a-00 march 2011 www.richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.350 0.008 0.014 d 1.900 2.100 0.075 0.083 d2 1.550 1.650 0.061 0.065 e 1.900 2.100 0.075 0.083 e2 0.950 1.050 0.037 0.041 e 0.650 0.026 l 0.200 0.300 0.008 0.012 w-type 6sl dfn 2x2 package d 1 e a3 a a1 e b l d2 e2 see detail a 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options
RT8057A 12 ds8057a-00 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringemen t of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed b y richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com tsot-23-5 surface mount package dimensions in millimeters dimensions in inches symbol min max min max a 0.700 1.000 0.028 0.039 a1 0.000 0.100 0.000 0.004 b 1.397 1.803 0.055 0.071 b 0.300 0.559 0.012 0.022 c 2.591 3.000 0.102 0.118 d 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024 a a1 e b b d c h l

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